CPAR-ECG: A COGNITIVE POWER-AWARE RECONFIGURABLE ARCHITECTURE FOR LOW-LATENCY WEARABLE CARDIAC ANALYTICS

Abstract

Continuous ECG monitoring requires a computational framework that can maintain high diagnostic accuracy while accommodating the power and latency constraints of wearable devices. We present a power-aware cognitive computing architecture deployed on reconfigurable SoC, which is tailored to the real-time cardiac status for dynamic adjust analytical depth. The structures of adaptive preprocessing, cognitive feature selection and a hybrid FPGA–ARM execution pipeline achieve the efficiency and context awareness on ECG analysis. A recurrent strategy which combine recurrence quantification analysis (RQA) and superlet-based time–frequency transforms, followed by a low-frequency atrial-fibrillation filtering is learned to extract multi-representation features onto the quantized masked autoencoder whose latent embedding drive a multiscale CNN with attention fusion. The cognitive controller dynamically monitors rhythm variation and signal complexity to control sample rate exploitation, inference frequency tuning and hardware activation for fast mode switching between low-power operation mode and high-precision operation modes. Experimental results show that our proposed FPGA-based design could provide better diagnosis abilities, and achieves as high as 98.4% diagnostic accuracy with an end-to-end delay of about 1.2ms, while introducing less energy consumption compared to CPU and GPU baselines by over 60%. The proposed CPAR-ECG approach introduces a scalable design framework for power effective in-situ bio-signal analytics computation on next generation wearable cardiac monitoring devices.