INTELLIGENT PERFORMANCE OPTIMIZATION OF SQRT-CSLA ARCHITECTURE USING GRAPH NEURAL NETWORKS AND BEC LOGIC

Abstract

This research introduces a data-aware deep learning optimization framework using Graph Neural Networks (GNNs) for enhancing the performance of the Square-Root Carry Select Adder (SQRT-CSLA) architecture in VLSI system design. Extending deterministic circuit-level optimizations, the proposed approach enables context-sensitive and input-driven optimization by learning complex interactions between circuit topology, switching activity, and performance metrics. The SQRT-CSLA was modeled at the gate level as a graph, where logic gates were represented as nodes and signal dependencies as edges, facilitating effective GNN-based learning. Post-synthesis simulation data, including power consumption, propagation delay, and switching activity, were employed to train the GNN to capture nonlinear relationships among structural and data-dependent characteristics of the circuit. Unlike conventional static or rule-based optimization techniques, the proposed method accurately identified switching-intensive paths and redundancy-prone logic regions that are difficult to detect through analytical analysis alone. Guided by GNN inference, adaptive optimization strategies such as selective logic pruning, gate resizing, and operand isolation were applied to critical carry paths and Binary-to-Excess-1 Converter (BEC) logic. This intelligent optimization process resulted in significant reductions in average power dissipation and improved delay uniformity under realistic operating conditions. Furthermore, the framework demonstrated strong scalability across different operand word lengths and technology nodes, highlighting its robustness and generalization capability. By embedding deep learning intelligence into the VLSI optimization workflow, the proposed approach advances energy-efficient and high-performance arithmetic circuit design.